Qualcomm LogoLayout Checker

User Guide

Qualcomm Layout Checker is a web browser-based interface that enables the setup and simulation of PCB/PKG layouts for Electrical Design Rule Checking using the HyperLynx DRC tool from Siemens EDA.

  • The tool runs HyperLynx DRC VX.2.12 in the backend for simulation.
  • Generates an Excel report containing violation details with snapshots of the violated areas.
  • It reduces the engineering time required to install the HyperLynx DRC tool on the user’s machine, manually import the designs, and set up the simulation for Electrical DRC, making this tool very efficient and time-saving.
  • HyperLynx DRC also supports custom rule development using Python or VBScript, which can increase the coverage of Electrical DRC and further reduce the sign-off time.
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