General

What are the PCB file formats supported?

Cadence .BRD, Cadence .SPD and tool independent format - ODB++.

What is the recommendation on the board configuration description?

You can use any name of your choice, but avoid use of special characters.

Is it recommended to do simulations with all the devices at once?

Yes, particularly when there are shared rails between multiple devices and have cross-impedance, effective impedance and voltage drop specifications for the ports from multiple devices. If there is none, simulation can be run for individual rails or few selected ones, based on the areas of interest.

How much time it takes for the simulation?

It depends on the PCB size, complexity, and the number of rails under simulation. For a rail, it can range from 15 minutes to 2 hours. You will be able to see the report (PDF) only when all the rail simulations are completed.

What is the allowed format for the custom capacitor models?

S-parameter files

What if there is no matching VRM port found in the port selection?

If there is only an AC specification given for that rail, a VRM is not provided, and you will see this message. It is okay to ignore this message and move forward. However, if a DCR specification also exists, it is recommended to go back and check the selected VRM devices. If the VRM is a third-party device, try using the cap VRM as a substitute.

How to select a capacitor for VRM?

Capacitors placed closest to the VRM output pin should be selected. This will ensure the measured DCR is closer to the actual value.

What to do if certain functions are not being used from the device?

You can deselect those ports or rails altogether if they are not being used. For example, if a rail supplies voltage to all the camera PHYs and only partial PHYs are being used, you can deselect the PHY ports that are not being used. If the camera PHYs are not being used at all, you can deselect the complete rail altogether.

What is a rail and what is a port?

Rails are the power nets driving the load. A port is an input/output with the definition of device pins; the exact pins (positive and negative) are mentioned in the processor device’s -1P document (PDN Specifications).

How to understand the plot?

Plots provide PDN impedance response over frequency with the red-colored mask; measured PDN impedance must be smaller than the mask across the entire range of frequencies of the mask.

I get a message about a mismatch in stack-up between the board file and board configuration.

If the stack-up layer name or number of layers has changed compared to the previous run where the board configuration info was used, this message is shown. In this case, allow the overwrite of the board configuration.

Do we need to assign models for PMIC and SOC?

No, models should not be assigned for the PMIC and the SOC.

What is the temperature setting at which the simulation is run?

By default, it is 25°C. However, you can alter the temperature in the stack-up step. Note that only copper conductivity is altered based on the temperature selection.

I get a huge list of components for which the model needs to be assigned; some of them seem irrelevant.

This can happen if there is an electrical path (through resistors) between the SOC rails and VPH_PWR. To avoid a big list of components, delete the components forming the bridge to VPH_PWR (just temporarily for simulation) and submit for simulation

Where can I get details on Vdrop calculations?

Refer to 80-VT310-90 PDN Vdrop Methodology.

FAQ